Today, in conventional SRAM devices, 6-transistor CMOS SRAM cells are configured using planar metal-oxide silicon (MOS) field effect transistors.
However, miniaturization of the device dimensions, to improve integration density and operation speed, increases variation in the characteristics of the devices produced. The variation obviously affects the operational stability of the SRAM. That is, the performances of the respective devices deviate randomly from the design target, so that mismatch occurs and bistability, which is indispensable for memory retention, is reduced. The variation in the device characteristics may eventually lead to malfunction, so that the production yield will be lowered and reliability of the information systems will be lowered.
As an index for evaluating bistability, noise margin can be employed. The noise margin is defined as the maximum voltage of the noise amplitude which is allowed to be superposed on memory nodes. A sufficient noise margin for a read operation, i.e., a read margin, is the most difficult to ensure. The above-mentioned mismatch between the devices reduces the read margin. Therefore, the SRAM device is designed so that the noise margin is as large as possible. This ensures a sufficient noise margin even with a large variation in the performance of the devices as produced.
This read margin is essentially in a trade-off relationship with a read current which determines read speed. That is, a cell with a larger read margin has a slower read speed, while a cell with a faster read speed has a smaller read margin. The selection transistor or pass gate connecting to a node holding a potential corresponding to the logic ‘0’ is the cause of the trade-off relationship.
This trade-off between the read margin and the read current reduces the operating voltage of the SRAM because the overdrive voltage approaches the magnitude of threshold-voltage variation of the selection transistor by reducing power supply voltage when some selection transistors are on while others are not. In other words, the read current may vary by orders of magnitude. As a result, cells which cannot be read in a practical time period but have a larger noise margin and cells which can be read at high speed but have a smaller noise margin are concurrently present in the same array.
Patent Documents 1 to 3 disclose SRAM devices which use a four-terminal double gate field effect transistor, of which two gates of the double gate field effect transistor are separated from each other, as the selection transistor. These SRAM devices can adjust a threshold voltage of the selection transistor in order to increase the respective noise margins either in the read operation or in the write operation. However, there is still the trade-off relationship between the noise margin and the read speed in the read operation.
Accordingly, determining the operational sped based on a cell with the highest read speed results in cells which cannot be read, while determining the read speed based on the cell with the highest stability results in a significant decrease in the speed.    Patent Document 1: JP 2007-20110    Patent Document 2: U.S. Pat. No. 7,511,989    Patent Document 3: WO 2008/114716